In the manufacture of various products, electrically conductive material and dielectric material are formed on, in, or as part of, a silicon substrate such that regions of the electrically conductive material are separated by regions of dielectric material from other regions of the electrical conductive material to define electrical elements (e.g., transistors, capacitors, resistors) and electrical interconnections between electrical elements. Substrates including electrically conductive regions separated by a dielectric region are sometimes referred to herein as electronic devices. Electronic components such as microprocessors and memory chips for computers and other devices like flat panel displays are well-known examples of such products.
During operation of an electronic device, the flow of current through an electrical interconnection can cause electromigration which can result in deformation of the electrical interconnection, in particular at an interface with adjacent material. Electromigration is used herein to refer to the movement of atoms of an electrically conductive material as a result of current flow through the electrically conductive material. Such deformation can result in undesirable current leakage or current flow inhibition. As the characteristic dimension of electrical interconnections of electronic devices becomes smaller, the increased current density flowing through those electrical interconnections renders electromigration even more of a problem.
A semiconductor device is an electronic device in which the substrate comprises a semiconductor material or materials. The semiconductor device can include for example electrically conductive regions and dielectric regions formed over another electrically conductive region. The electrically conductive regions can be, for example, interconnections between the electrically conductive region and other electrically conductive material to be subsequently formed as part of the semiconductor device. In current semiconductor devices, copper is commonly used to form electrically conductive regions and a silicon dioxide-based material (e.g., FSG, SiCOH, porous SiCOH, MSQ, etc.) is commonly used to form dielectric regions. Additionally, in current semiconductor devices, the dielectric region often includes a hard mask layer (which is often formed of a silicon-based material (e.g., SiCx, SiNx, SiCxNy, where the variables x, y, and z represent values as appropriate to desired compositions) formed at a top portion of the dielectric region.
A semiconductor device can include a dielectric barrier layer that is a layer of dielectric material in a semiconductor or other electronic device formed non-selectively on both electrically conductive regions and dielectric regions that separate those electrically conductive regions, after planarization of the top of the electrically conductive regions and dielectric regions. The dielectric barrier layer is used to inhibit diffusion of material from the electrically conductive regions into adjacent regions (in particular, into the bulk dielectric material subsequently formed over the electrically conductive regions) of the semiconductor device.
In current semiconductor devices, compositions including silicon together with carbon and/or nitrogen (e.g., SiCx, SiNx, SiCxNy) are commonly used to form the dielectric barrier layer. Since these materials have a higher dielectric constant than the dielectric materials that could otherwise be used, an undesirable consequence of the presence of a dielectric barrier layer is that the capacitance associated with the device structure is increased, which can increase power consumption and/or decrease speed of operation of the semiconductor device.
Further, conventional implementations of a dielectric barrier layer do not adhere well to conventional implementations of electrically conductive regions in semiconductor devices.
Consequently, these conventional dielectric barrier layers do little to inhibit electromigration in the electrically conductive regions, which commonly is initiated at the interface between the electrically conductive regions and the dielectric barrier layer.
In view of the foregoing, there is a need for improved inhibition of electromigration in electrically conductive regions of semiconductor and other electronic devices and, in particular, at interfaces of electrically conductive regions with adjacent regions formed of other material. There is also a need for reduction in capacitance of the structure formed in the vicinity of the electrically conductive regions of semiconductor and other electronic devices, while adequately maintaining a barrier to diffusion of material from the electrically conductive regions into adjacent regions formed of other material. These needs have and will likely continue to become increasingly strong as the characteristic dimension of features in electronic devices becomes smaller.
To inhibit electromigration at the interface between electrically conductive regions and a dielectric barrier layer of a semiconductor device, a layer of material has been selectively formed on the electrically conductive regions before forming the dielectric barrier layer. Such a selectively formed layer can be referred to as, for example, a capping layer. Capping layers have been formed under conventional processes using various materials and processes. For example, a capping layer has been formed by selectively depositing an appropriate material on electrically conductive regions. A metallic material is often deposited by an electroless metallization process because this process can be catalyzed by the metallic regions of the surface, providing some inherent selectivity.
For instance, electroless deposition has been used to selectively deposit a metal alloy (e.g., an alloy of cobalt, tungsten and phosphorous; an alloy of cobalt and boron; or an alloy of nickel, molybdenum and phosphorous) on copper regions. An approach of this type is described in “High Reliability Cu Interconnection Utilizing a Low Contamination CoWP Capping Layer,” by T. Ishigami et al., Proceedings of the 2004 IEEE International Interconnect Technology Conference, Jun. 7-9, 2004, pp. 75-77. Chemical vapor deposition has also been used to selectively deposit tungsten on copper regions. An approach of this type is described in “A Robust, Deep-Submicron Copper Interconnect Structure using Self-Aligned Metal Capping Method,” by T. Saito et al., Proceedings of the 2004 IEEE International Interconnect Technology Conference, Jun. 7-9, 2004, pp. 36-38. However, the selectivity of these approaches is inadequate to inhibit formation of capping layer material (which is electrically conductive) on dielectric regions to an extent that prevents unacceptable current leakage between electrically conductive regions separated by those dielectric regions. This may be due, at least in part, to residual material from the electrically conductive regions that is left on the dielectric regions after planarization (e.g., chemical mechanical polishing (CMP)) of the exposed surfaces. This residual metallic contamination on the dielectric regions may provide nucleation sites for the capping layer material (which is chosen for its affinity for forming on the material of the electrically conductive regions). This can significantly reduce preferential formation of the capping layer material on the electrically conductive regions as compared to the dielectric regions.
A capping layer has also been formed under conventional processing by chemically modifying a top part of each of the electrically conductive regions. For example, a capping layer has been formed by chemically modifying the top parts of copper regions using silicidation and nitridation. An approach of this type is described in “Integration and performance of an alternative approach using copper silicide as a self-aligned barrier for 45 nm technology node Cu interconnects,” by L. G. Gosset et al., Proceedings of the 2004 IEEE International Interconnect Technology Conference, Jun. 7-9, 2004, pp. 15-17. However, the capping layer formed in this way undesirably increases resistance in the electrically conductive regions.
It has also been proposed to form a capping layer of organic material on electrically conductive regions of a semiconductor device to inhibit electromigration at the surfaces of the electrically conductive regions. The use of organic material, which is a very poor electrical conductor, eliminates the potential for unacceptable current leakage between electrically conductive regions resulting from the presence of the capping layer, even if the processes and materials used to form the organic layer are not particularly selective in preferentially forming the organic layer on electrically conductive regions. U.S. Patent Application Publication Number US-2004-0203192-A1 describes such an approach in which a self-assembled organic monolayer (in particular, a thiolate self-assembled monolayer) is covalently bonded to metallic regions. However, it is believed that the thiolate self-assembled monolayers described therein may not produce, when formed on copper, a thermally stable capping layer that remains continuous and defect-free under operating conditions of the semiconductor device. Therefore, the capping layer formed in this manner may not adequately inhibit electromigration, or provide an adequate copper diffusion barrier that can enable elimination of the dielectric barrier layer from the semiconductor device.
Furthermore, it is becoming desirable to use porous dielectric materials in electronic devices (which may or may not have a hard mask layer formed thereon), particularly semiconductor devices used in the production of electronic components. A porous material, in this context a porous dielectric material, is particularly susceptible to diffusion of other material therein. For example, a dielectric region made of a porous dielectric material is particularly susceptible to diffusion therein of capping layer material; especially when the capping layer material is a metallic material, as is often the case, diffusion of capping layer material into a dielectric region increases the likelihood of unacceptable current leakage.
Additionally, as described above, residual material from electrically conductive regions that is left on a dielectric region after planarization (e.g., chemical mechanical polishing) of the exposed surfaces of the electrically conductive regions and dielectric region can provide nucleation sites for the capping layer material, thus significantly reducing preferential formation of the capping layer material on the electrically conductive regions during formation of a capping layer. A dielectric region made of a porous dielectric material is particularly susceptible to diffusion therein of such residual material, thus exacerbating this problem. Consequently, there is a need for materials and processes that are compatible with a variety of substrates and functionalize or normalize the substrate for compatibility with subsequent processes typically applied to the substrate while reducing the effects of electromigration and diffusion.